Field effect transistors (FETs) are used to a great extent in various logic and control circuits because of their low power requirements. As is known, many logic and control circuits use complementary devices to further reduce the power consumed in the circuits. Because of this extensive use, there is a need to make FETs smaller so that larger numbers of them can be incorporated into integrated circuits and the like. Also, by making the FETs smaller, especially with shorter gates, the operating frequency can be much higher and the devices can be used in high speed digital circuits and the like. Some of the smallest FETs are heterostructure FETs (HFETs), including heterostructure insulated gate field effect transistors (HIGFETs).
Prior art HFETs and especially p-channel HFETs cannot practically be made with very short gate lengths due to severe short channel effects such as high output conductance and subthreshold currents. Generally, prior art HFETs are constructed with a buffer layer on the substrate. Such buffer layers grown by a molecular beam epitaxy process are unintentionally doped, generally p-type. The buffer layers are p-doped about 1-3 E14 cm.sup.-3. Subthreshold currents are determined by conduction through the buffer layers. While the subthreshold of N-channel devices is controlled reasonably well for devices of gate lengths, Lg, down to 0.3 .mu.ms, due to the potential barrier resulting from the P-buffer which confines electrons, P-channel devices suffer severe short channel effects from conduction between the source and drain contacts.
For P-channel devices this is one of the key problems that prevents the successful fabrication of prior art submicron devices, especially complementary devices. As gate dimensions are reduced in these devices, from 1 .mu.m to lower levels (e.g. 0.5 .mu.m), the subthreshold leakage currents increase almost exponentially from near nano-amperes to several hundred nano-amperes, or in some cases microamperes when the gate length is at 0.5 .mu.m. Subthreshold slopes also increase substantially to several hundred millivolts per decade, and the devices do not pinch-off at all. Also, noise margins are severely degraded. Thus, these prior art devices become useless for complementary logic circuits as they are made smaller.
Accordingly, it would be advantageous to provide HFETs which could be fabricated in submicron ranges with improved operating characteristics.
It is a purpose of the present invention to provide a new and improved HFET and method of fabrication.
It is another purpose of the present invention to provide a new and improved HFET which can be manufactured in submicron ranges with substantially reduced subthreshold leakage currents.
It is still another purpose of the present invention to provide a new and improved P-channel HFET which can be manufactured with gate lengths under 0.5 .mu.m and subthreshold leakage currents in the nanoamperes.
It is a further purpose of the present invention to provide a new and improved method of fabricating HFETs which can be used to manufacture complementary HFETS.